1. Field of the Invention
The present invention generally relates to a method and apparatus for enhancing error detection in a microprocessor, and more particularly to a method and apparatus for enhancing error detection in a microprocessor by using a second dependency matrix.
2. Description of the Related Art
Microprocessors using a dependency matrix to do dependency tracking present a special problem for Reliability, Availability, and Serviceability (RAS) checking. Because the microprocessor arrays are not read or written normally, there is no easy way to check for errors. Furthermore, additional structures such as the picker (age array) may also be difficult to check for soft errors. This presents a special problem if the dependency matrix is to be the only location where dependencies are tracked.
Conventional methods for error checking consist of two methods. The first method is duplicating a primary dependency matrix and a issue logic, which is a logic that is being checked that may actually cause an issue. This requires a great deal of physical area because the issue logic (including picker) can be quite large. Also, the issue logic can be very complicated, and duplicating it in its entirety means also duplicating any bugs present.
The second method consists of creating specialized issue checking logic for each type of dependency tracked by the dependency matrix. This is also undesirable because a dependency matrix may track a large number of different types of dependencies, each requiring an independently designed issue checker. This increases design risk and requires increased design effort.
Thus, a method is desired to check a primary dependency matrix and associated issue logic that does not involve duplicating the issue logic and that also does not require a different check be designed for each type of dependency tracked by the primary dependency matrix.